Method for manufacturing metal-insulator-metal capacitor structure

ABSTRACT

A method for manufacturing the MIM capacitor structure is provided. A first damascene electrode layer is formed in the first opening formed in a first dielectric layer. An insulating barrier layer is formed to cover the first dielectric layer and the first damascene electrode layer. A second opening and a third opening are formed in the second dielectric layer formed on the insulating barrier layer. The second opening and the third opening are located above the first damascene electrode layer to expose a portion of the insulating barrier layer therefrom. The insulating barrier layer in the third opening is removed to expose a portion of the first damascene electrode layer. A second damascene electrode layer is formed in the second opening to be contacted with the insulating barrier layer and a dual damascene structure is formed in the third opening to be contacted with the first damascene electrode layer.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of U.S. patent application Ser. No.13/292156, filed on Nov. 9, 2011, which is currently pending. Theentirety of the above-mentioned patent application is herebyincorporated by reference herein and made a part of this specification.

FIELD OF THE INVENTION

The present invention relates to a capacitor structure, and particularlyto a method for manufacturing a metal-insulator-metal (MIM) capacitorstructure.

BACKGROUND OF THE INVENTION

Generally, a MIM capacitor comprises two metal electrodes separated byan insulator. The MIM capacitor has advantages of small size, stablecapacitor value and little parasitic effect, and so on.

With the development of the integrated circuit technology, the MIMcapacitor has been widely used so as to improve the performance of theintegrated circuit. Currently, in order to electrically connect the MIMcapacitor with other electronic components, the MIM capacitor is usuallyintegrated with an interconnection structure. However, in a conventionalprocess for integrating the MIM capacitor with the interconnectionstructure, it is necessary to form a number of insulating layers and anumber of metal layers. Thus, the conventional process for integratingthe MIM capacitor with the interconnection structure a number ofdepositing steps and etching steps, thereby increasing the productioncost and causing the final integrated structure to be complicated.

SUMMARY OF THE INVENTION

The present invention also provides a method for manufacturing a MIMcapacitor, which has a simple process so as to reduce the productioncost.

The present invention provides a method for manufacturing a MIMcapacitor. At first, a first opening is formed in a first dielectriclayer. A first damascene electrode layer is filled in the first opening.Next, an insulating barrier layer is formed to cover the firstdielectric layer and the first damascene electrode layer. Next, a seconddielectric layer is formed on the insulating barrier layer. Next, asecond opening and a third opening are formed in the second dielectriclayer formed on the insulating barrier layer. The second opening and thethird opening are located above the first damascene electrode layer toexpose a portion of the insulating barrier layer therefrom. Next, theinsulating barrier layer in the third opening is removed to expose aportion of the first damascene electrode layer. Next, a second damasceneelectrode layer is formed in the second opening to be contacted with theinsulating barrier layer and a dual damascene structure is formed in thethird opening to be contacted with the first damascene electrode layer.

In one embodiment of the present invention, the step of filling thefirst damascene electrode layer in the first opening includes: forming ametal layer on the first dielectric layer and filling the metal layerinto the first opening; and removing a portion of the metal layeroutside the first opening to form the first damascene electrode layer.

In one embodiment of the present invention, a chemical mechanicalpolishing process is applied to remove the portion of the metal layeroutside the first opening to form the first damascene electrode layer.

In one embodiment of the present invention, the metal layer is a copperlayer.

In one embodiment of the present invention, the step of forming theinsulating barrier layer to cover the first dielectric layer and thefirst damascene electrode layer includes: forming the insulating barrierlayer in a single layer structure, and a material of the insulatingbarrier layer is selected from a group consisting of silicon nitride(SiN), silicon carbide (SiC), silicon carbonitride (SiCN) and siliconoxynitride (SiON).

In one embodiment of the present invention, the step of forming theinsulating barrier layer to cover the first dielectric layer and thefirst damascene electrode layer includes forming the insulating barrierlayer in a multilayer structure.

In one embodiment of the present invention, forming the insulatingbarrier layer in the multilayer structure includes the following steps.At first, a first insulating layer is formed on the first dielectriclayer, and a material of the first insulating layer is selected from agroup consisting of silicon nitride (SiN), silicon carbide (SiC),silicon carbonitride (SiCN) and silicon oxynitride (SiON). Next, asecond insulating layer is formed on the first insulating layer, and amaterial of the second insulating layer is selected from a groupconsisting of undoped silicate glass (USG), tantalum oxide (Ta₂O₅),zirconium oxide (ZrO₂) and aluminum oxide (Al₂O₃).

In one embodiment of the present invention, forming the third opening inthe second dielectric layer includes: forming at least one via; andforming one trench located above and communicated with the at least onevia.

In one embodiment of the present invention, the third opening is formedby a trench first process, a via first process or a self-alignedprocess.

In one embodiment of the present invention, the step of removing theinsulating barrier layer in the third opening to expose the portion ofthe first damascene electrode layer includes the following steps. Atfirst, a patterned mask layer is formed on the second dielectric layerto cover the second opening and to expose the third opening. Next, theportion of the insulating barrier layer exposed from the patterned maskis removed. Next, the patterned mask layer is removed.

In one embodiment of the present invention, the step of forming a seconddamascene electrode layer in the second opening and forming a dualdamascene structure in the third opening includes the following steps.At first, a metal layer is formed on the second dielectric layer and isfilled into the second opening to be contacted with the insulatingbarrier layer and into the third opening to be contacted with the firstdamascene electrode layer. Then, a portion of the metal layer outsidethe second opening and the third opening is removed to form the seconddamascene electrode layer and the dual damascene structure.

In one embodiment of the present invention, a chemical mechanicalpolishing process is applied to remove the portion of the metal layeroutside the second opening and the third opening to form the seconddamascene electrode layer and the dual damascene structure.

In one embodiment of the present invention, the metal layer is a copperlayer.

In the method for manufacturing the MIM capacitor according to theembodiments of the present invention, the first damascene electrodelayer and the second damascene electrode layer are both formed by adamascene process and are separated by the insulating barrier layer. Theinsulating barrier can serve as not only an insulator of the MIMcapacitor, but also an etch stop layer during forming the seconddamascene electrode layer. Thus, the MIM capacitor has a simplerstructure, thereby reducing the production cost. The MIM capacitorfurther includes the dual damascene structure formed in the seconddielectric layer and the insulating barrier layer and electricallyconnected to the first damascene electrode layer. The dual damascenestructure and the second damascene electrode layer can be formed in acommon step. Thus, the process of integrating the MIM capacitor with aninterconnection structure can be simplified, thereby reducing theproduction cost.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more readily apparent to thoseordinarily skilled in the art after reviewing the following detaileddescription and accompanying drawings, in which:

FIGS. 1A-1E illustrate a process flow of a method for manufacturing aMIM capacitor in accordance with a first embodiment of the presentinvention.

FIG. 2 illustrates a schematic view of a MIM capacitor with aninterconnection structure fabricated in accordance with the firstembodiment of the present invention.

FIGS. 3A-3H illustrate a process flow of a method for manufacturing aMIM capacitor in accordance with a second embodiment of the presentinvention.

FIG. 4 illustrates a schematic view of a MIM capacitor with aninterconnection structure fabricated in accordance with the secondembodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will now be described more specifically withreference to the following embodiments. It is to be noted that thefollowing descriptions of preferred embodiments of this invention arepresented herein for purpose of illustration and description only. It isnot intended to be exhaustive or to be limited to the precise formdisclosed.

FIGS. 1A-1E illustrate a process flow of a method for manufacturing aMIM capacitor in accordance with a first embodiment of the presentinvention.

Referring to FIG. 1A, in the present embodiment, for example, a firstdamascene electrode layer 120 is formed in a first dielectric layer 110by a damascene process. In detail, at first, a first opening 112 isformed in the first dielectric layer 110. Then, a metal layer (e.g., acopper layer) is formed on the first dielectric layer 110 and filledinto the first opening 112. Thereafter, a chemical mechanical polishingprocess is applied to the metal layer so that a portion of the metallayer outside the first opening 112 is removed. Thus, the firstdamascene electrode layer 120 is formed and filled in the first opening112. In the present embodiment, the first damascene electrode layer 120is a copper damascene layer.

Referring to FIG. 1B, next, an insulating barrier layer 130 is formed tocover the first dielectric layer 110 and the first damascene electrodelayer 120. The insulating barrier layer 130 is a single layer structure.A material of the insulating barrier layer 130 can include siliconnitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN),silicon oxynitride (SiON) or other high dielectric constant materials.In the present embodiment, a dielectric constant of the insulatingbarrier layer 130 is, for example, 5. A thickness of the insulatingbarrier layer 130 is in a range from 200 to 1500 angstroms.

Referring to FIG. 1C, next, a second dielectric 140 is formed on andcontacted with the insulating barrier layer 130. In the presentembodiment, a material of the second dielectric 140 and a material ofthe first dielectric layer 110 are, for example, oxide.

Referring to FIG. 1D to FIG. 1E, in the present embodiment, for example,a second damascene electrode layer 150 is formed in the seconddielectric layer 140 by a damascene process. In detail, at first,referring to FIG. 1D, a second opening 142 is formed in the seconddielectric layer 140 and is located above the first damascene electrodelayer 120 so as to expose a portion of the insulating barrier layer 130.

During forming the second opening 142 in the second dielectric layer140, the insulating barrier layer 130 can serve as an etch stop layer.That is, due to the etching selectivity of the second dielectric layer140 and the insulating barrier layer 130, the etching process forforming the second opening 142 in the second dielectric layer 140 willstop on the insulating barrier layer 130. Thus, after the second opening142 is formed, a portion of insulating barrier layer 130 is exposed fromthe second opening 142.

Referring to FIG. 1E, next, a metal layer (e.g., a copper layer) isformed on the second dielectric layer 140 and filled into the secondopening 142 to cover the portion of the insulating barrier layer 230exposed from the second opening 142. Then, a chemical mechanicalpolishing process is applied to the metal layer so that a portion of themetal layer outside the second opening 142 is removed. Thus, the seconddamascene electrode layer 150 contacted with the insulating barrierlayer 130 is formed and filled in the second opening 142. In the presentembodiment, the second damascene electrode layer 150 is a copperdamascene layer.

After the second damascene electrode layer 150 is formed, the MIMcapacitor 100 is manufactured by the method in accordance with the firstembodiment. In detail, the MIM capacitor 100 includes the firstdielectric layer 110, the first damascene electrode layer 120, theinsulating barrier layer 130, the second dielectric layer 140 and thesecond damascene electrode layer 150. The first damascene electrodelayer 120 is formed in the first dielectric layer 110. The insulatingbarrier layer 130 covers the first dielectric layer 110 and the firstdamascene electrode layer 120, and is the single layer structure. Thesecond dielectric layer 140 is formed on and contacted with theinsulating barrier layer 130. The second damascene electrode layer 150is formed in the second dielectric layer 140, is located above the firstdamascene electrode layer 120 and is contacted with the insulatingbarrier layer 130.

Particularly, in the MIM capacitor 100, the insulating barrier layer 130can further serve as a capacitor dielectric layer between the firstdamascene electrode layer 120 and the second damascene electrode layer150. In other words, in the method for manufacturing the MIM capacitor100, it is not necessary to deposit extra dielectric layers between thetwo electrode layers (i.e., the first damascene electrode layer 120 andthe second damascene electrode layer 150). Thus, the method can reducethe production cost of the MIM capacitor and manufacture the MIMcapacitor 100 with a simple structure.

It is noted that, during forming the second opening 142, a portion ofthe insulating barrier layer 130 can be etched due to an over etcheffect. Thus, after forming the second opening 142, a final thickness ofthe insulating barrier layer 130 is determined by an original depositionthickness of the insulating barrier layer 130 and an etching rate of anetchant for etching the second dielectric layer 140 to the insulatingbarrier layer 130.

According to the method for manufacturing the MIM capacitor 100, it isalso noted that, the fabrication of the MIM capacitor 100 can beintegrated with a fabrication of an interconnection structure. FIG. 2illustrates a schematic view of a MIM capacitor with an interconnectionstructure of an integrated circuit. Referring to FIG. 2, in the presentembodiment, an interconnection structure 30, for example, a dualdamascene interconnection structure, is shown, which includes conductivewire layers 31, 32 and contact plugs 33, 34 electrically connecting thefirst conductive layers 31, 32. To integrate the process, theinterconnection structure 30 is formed in the first dielectric layer 110and the second dielectric layer 140. The conductive wire layer 31 andthe contact plug 33 can be formed in the process of forming the firstdamascene electrode layer 120. The conductive wire layer 32 and thecontact plug 34 can be formed in the process of forming the seconddamascene electrode layer 150. It is noted that, the insulating barrierlayer 130 may not formed in the region for forming the interconnectionstructure 30.

FIGS. 3A-3H illustrate a process flow of a method for manufacturing aMIM capacitor in accordance with a second embodiment of the presentinvention.

Referring to FIG. 3A, in the present embodiment, for example, a firstdamascene electrode layer 220 is formed in a first dielectric layer 210by a damascene process. In detail, at first, a first opening 212 isformed in the first dielectric layer 210. Then, a metal layer (e.g., acopper layer) is formed on the first dielectric layer 210 and filledinto the first opening 212. Thereafter, a chemical mechanical polishingprocess is applied to the metal layer so that a portion of the metallayer outside the first opening 212 is removed. Thus, the firstdamascene electrode layer 220 is formed and filled in the first opening212. In the present embodiment, the first damascene electrode layer 220is a copper damascene layer.

Referring to FIG. 3B, next, an insulating barrier layer 230 is formed tocover the first dielectric layer 210 and the first damascene electrodelayer 220. The insulating barrier layer 230 can be a single layerstructure. A material of the insulating barrier layer 230 can includesilicon nitride (SiN), silicon carbide (SiC), silicon carbonitride(SiCN), silicon oxynitride (SiON) or other high dielectric constantmaterials. A thickness of the insulating barrier layer 130 is in a rangefrom 200 to 1500 angstroms. The insulating barrier layer 230 can also bea multilayer structure, for example, including a first insulating layer(not shown) and a second insulating layer (not shown). The firstinsulating layer is formed on the first dielectric layer 210 and thefirst damascene electrode layer 220 and the second insulating layer isformed on the first insulating layer. A material of the first insulatinglayer is selected from a group consisting of silicon nitride (SiN),silicon carbide (SiC), silicon carbonitride (SiCN) and siliconoxynitride (SiON). A material of the second insulating layer is selectedfrom a group consisting of undoped silicate glass (USG), tantalum oxide(Ta₂O₅), zirconium oxide (ZrO₂) and aluminum oxide (Al₂O₃). A thicknessof the first insulating layer is in a range from 200 to 1500 angstroms.A thickness of the second insulating layer is in a range from 100 to1000 angstroms.

Referring to FIG. 3C, next, a second dielectric 240 is formed on andcontacted with the insulating barrier layer 230. In the presentembodiment, a material of the second dielectric 240 and a material ofthe first dielectric layer 210 are, for example, oxide. The method formanufacturing the MIM capacitor in the second embodiment is similar tothe method for manufacturing the MIM capacitor in the first embodimentexcept the following steps after forming the second dielectric 240.

Referring to FIG. 3D to FIG. 3H, in the present embodiment, for example,a second damascene electrode layer 250 is formed in the seconddielectric layer 240 by a damascene process and a dual damascenestructure 260 is formed in the second dielectric layer 240 and theinsulating barrier layer 230 by a dual damascene process. It is notedthat, in fact, the second damascene electrode layer 250 and the dualdamascene structure 260 are formed in a common damascene process.

In detail, referring to FIG. 3D, a second opening 242 and a thirdopening 244 are formed in the second dielectric layer 240 and arelocated above the first damascene electrode layer 220 so as to expose aportion of the insulating barrier layer 230, respectively. The thirdopening 244 includes at least a via 246 and a trench 245 located aboveand communicated with the via 246. In the present embodiment, the thirdopening 244 includes one trench 245 and one via corresponding to the onetrench 245. In another embodiment, the third opening can also includesone trench and a number of vias. In other words, the number and thelocation of the trench 245 and the via 246 are determined by theinterconnection demand. It is noted that, the third opening 244 can beformed by a trench first process, a via first process or a self-alignedprocess, which are not described here.

For example, the second opening 242 and the third opening 244 can beformed by a photolithography process. During forming the second opening242 and the third opening 244 in the second dielectric layer 140, theinsulating barrier layer 230 can serve as an etch stop layer. That is,due to the etching selectivity of the second dielectric layer 240 andthe insulating barrier layer 230, the etching process for forming thesecond opening 242 and the third opening 244 in the second dielectriclayer 240 will stop on the insulating barrier layer 230. Thus, after thesecond opening 242 and the third opening 244 are formed, a portion ofinsulating barrier layer 230 is exposed from the second opening 242 andthe third opening 244, respectively.

It is noted that, during forming the second opening 242 and the thirdopening 244, a portion of the insulating barrier layer 230 can be etcheddue to an over etch effect. Thus, after forming the second opening 242and the third opening 244, a final thickness of the insulating barrierlayer 230 is determined by an original deposition thickness of theinsulating barrier layer 230 and an etching rate of an etchant foretching the second dielectric layer 240 to the insulating barrier layer230.

Next, the portion of the insulating barrier layer 230 exposed from thethird opening 244 is removed so as to expose a portion of the firstdamascene electrode layer 220, thereby forming the dual damasceneopening 262. In the present embodiment, referring to FIG. 3E, apatterned mask layer 270 is formed on the second dielectric layer 240 tocover the second dielectric layer 240 and the second opening 242 and toexpose the third opening 244. For example, a material of the patternedmask layer 270 can be a photoresist material.

Referring to FIG. 3F, next, the portion of the insulating barrier layer230 exposed from the patterned mask 270 is removed. For example, anetchant for etching the insulating barrier layer 230 is selected to etchthe insulating barrier layer 230 exposed from the patterned mask 270 sothat the portion of the insulating barrier layer 230 exposed from thepatterned mask 270 is removed so as to expose the portion of the firstdamascene electrode layer 220. It is noted that, other suitable methodfor removing the portion of the insulating barrier layer 230 exposedfrom the patterned mask 270 can also be used. Referring to 3G, next, thepatterned mask layer 270 is removed, thereby forming the dual damasceneopening 262 in the second dielectric layer 240 and the insulatingbarrier layer 230.

Referring to FIG. 3H, next, a metal layer (e.g., a copper layer) isformed on the second dielectric layer 240 and is filled into the secondopening 242 to cover the portion of the insulating barrier layer 230exposed from the second opening 242 and is filled into the dualdamascene opening 262 to cover the portion of the first damasceneelectrode layer 220 exposed from the dual damascene opening 262. Then, achemical mechanical polishing process is applied to the metal layer sothat a portion of the metal layer outside the second opening 242 and thedual damascene opening 262 is removed. Thus, the second damasceneelectrode layer 250 contacted with the insulating barrier layer 230 isformed and filled in the second opening 242, and the dual damascenestructure 260 electrically connected to the first damascene electrodelayer 220 is formed and filled in the dual damascene opening 262. In thepresent embodiment, the second damascene electrode layer 250 is a copperdamascene layer, and the dual damascene structure 260 is a copper dualdamascene layer. That is, a material of the second damascene electrodelayer 250 is identical to a material of the dual damascene structure260.

Still, referring to FIG. 3H, the MIM capacitor 200 is manufactured bythe method in accordance with the second embodiment. The MIM capacitor200 includes the first dielectric layer 210, the first damasceneelectrode layer 220, the insulating barrier layer 230, the seconddielectric layer 240, the second damascene electrode layer 250 and thedual damascene structure 260. The first damascene electrode layer 220 isfilled in the first dielectric layer 210. The insulating barrier layer230 is formed on the first dielectric layer 210 and the first damasceneelectrode layer 220. The second dielectric layer 240 is formed on theinsulating barrier layer 230. The second damascene electrode layer 250is formed in the second dielectric layer 240, is located above the firstdamascene electrode layer 220 and is contacted with the insulatingbarrier layer 230. The dual damascene structure 260 is formed in thesecond dielectric layer 240 and the insulating barrier layer 230, islocated above the first damascene electrode layer 220 and iselectrically connected to the first damascene electrode layer 220.

In the present embodiment, the second damascene electrode layer 250 andthe dual damascene structure 260 are formed at the same time by using adual damascene process. Thus, it is not necessary to deposit extradielectric layers and metal layers, thereby simplifying the MIMcapacitor 200 with the interconnection structure and reducing theproduction cost. Thus, the method can reduce the production cost of theMIM capacitor and manufacture the MIM capacitor 100 with a simplestructure. Furthermore, the insulating barrier layer 230 can furtherserve as an etch stop layer and a capacitor dielectric layer between thefirst damascene electrode layer 220 and the second damascene electrodelayer 250. In other words, in the method for manufacturing the MIMcapacitor 200, it is not necessary to deposit extra dielectric layersbetween the two electrode layers (i.e., the first damascene electrodelayer 220 and the second damascene electrode layer 250).

According to the method for manufacturing the MIM capacitor 200, it isalso noted that, the fabrication of the MIM capacitor 200 can beintegrated with a fabrication of an interconnection structure of anintegrated circuit. FIGS. 4 illustrate a schematic view of a MIMcapacitor with an interconnection structure of an integrated circuit.Referring to FIG. 4, in the present embodiment, an interconnectionstructure 40, for example, a dual damascene interconnection structure,is shown, which includes conductive wire layers 41, 42 and contact plugs43, 44 electrically connecting the conductive layers 41, 42. Tointegrate the process, the interconnection structure 40 is formed in thefirst dielectric layer 210 and the second dielectric layer 240. Thefirst conductive wire layer 41 and the contact plug 43 can be formed inthe process of forming the second damascene electrode layer 250 and thedual damascene structure 260, the second conductive wire layer 42 andthe contact plug 44 can be formed in the process of forming the firstdamascene electrode layer 220. It is noted that, the insulating barrierlayer 230 may not formed in the region for forming the interconnectionstructure 40.

In the MIM capacitor and the method for manufacturing the MIM capacitorof the present invention, the first damascene electrode layer and thesecond damascene electrode layer are both formed by a damascene processand are separated by the insulating barrier layer. The insulatingbarrier can serve as not only an insulator of the MIM capacitor, butalso an etch stop layer during forming the second damascene electrodelayer. Thus, the MIM capacitor has a simple structure, thereby reducingthe production cost. In another embodiment, the MIM capacitor canfurther includes the dual damascene structure formed in the seconddielectric layer and the insulating barrier layer and electricallyconnected to the first damascene electrode layer. The dual damascenestructure and the second damascene electrode layer can be formed in acommon step. Thus, the process of integrating the MIM capacitor with aninterconnection structure can be simplified, thereby reducing theproduction cost.

While the invention has been described in terms of what is presentlyconsidered to be the most practical and preferred embodiments, it is tobe understood that the invention needs not be limited to the disclosedembodiment. On the contrary, it is intended to cover variousmodifications and similar arrangements included within the spirit andscope of the appended claims which are to be accorded with the broadestinterpretation so as to encompass all such modifications and similarstructures.

What is claimed is:
 1. A method for manufacturing a MIM capacitor,comprising: forming a first opening in a first dielectric layer; fillinga first damascene electrode layer in the first opening; forming aninsulating barrier layer to cover the first dielectric layer and thefirst damascene electrode layer; forming a second dielectric layer onthe insulating barrier layer; forming a second opening and a thirdopening in the second dielectric layer, the second opening and the thirdopening being located above the first damascene electrode layer toexpose a portion of the insulating barrier layer therefrom; removing theinsulating barrier layer in the third opening to expose a portion of thefirst damascene electrode layer; and forming a second damasceneelectrode layer in the second opening to be contacted with theinsulating barrier layer and forming a dual damascene structure in thethird opening to be contacted with the first damascene electrode layer.2. The method as claimed in claim 1, wherein the step of filling thefirst damascene electrode layer in the first opening comprises: forminga metal layer on the first dielectric layer and filling the metal layerinto the first opening; and removing a portion of the metal layeroutside the first opening to form the first damascene electrode layer.3. The method as claimed in claim 2, wherein a chemical mechanicalpolishing process is applied to remove the portion of the metal layeroutside the first opening to form the first damascene electrode layer.4. The method as claimed in claim 2, wherein the metal layer is a copperlayer.
 5. The method as claimed in claim 1, wherein the step of formingthe insulating barrier layer to cover the first dielectric layer and thefirst damascene electrode layer comprises: forming the insulatingbarrier layer in a single layer structure, and wherein a material of theinsulating barrier layer is selected from a group consisting of siliconnitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN) andsilicon oxynitride (SiON).
 6. The method as claimed in claim 1, whereinthe step of forming the insulating barrier layer to cover the firstdielectric layer and the first damascene electrode layer comprises offorming the insulating barrier layer in a multilayer structure.
 7. Themethod as claimed in claim 6, wherein forming the insulating barrierlayer in the multilayer structure comprises: forming a first insulatinglayer on the first dielectric layer, and wherein a material of the firstinsulating layer is selected from a group consisting of silicon nitride(SiN), silicon carbide (SiC), silicon carbonitride (SiCN) and siliconoxynitride (SiON); and forming a second insulating layer on the firstinsulating layer, and wherein a material of the second insulating layeris selected from a group consisting of undoped silicate glass (USG),tantalum oxide (Ta₂O₅), zirconium oxide (ZrO₂) and aluminum oxide(Al₂O₃).
 8. The method as claimed in claim 1, wherein forming the thirdopening in the second dielectric layer comprising: forming at least onevia; and forming one trench located above and communicated with the atleast one via.
 9. The method as claimed in claim 8, wherein the thirdopening is formed by a trench first process, a via first process or aself-aligned process.
 10. The method as claimed in claim 1, wherein thestep of removing the insulating barrier layer in the third opening toexpose the portion of the first damascene electrode layer comprises:forming a patterned mask layer on the second dielectric layer to coverthe second opening and to expose the third opening; removing the portionof the insulating barrier layer exposed from the patterned mask; andremoving the patterned mask layer.
 11. The method as claimed in claim 1,wherein the step of forming a second damascene electrode layer in thesecond opening and forming a dual damascene structure in the thirdopening comprises: forming a metal layer on the second dielectric layerand filling the metal layer into the second opening to be contacted withthe insulating barrier layer and into the third opening to be contactedwith the first damascene electrode layer; and removing a portion of themetal layer outside the second opening and the third opening to form thesecond damascene electrode layer and the dual damascene structure. 12.The method as claimed in claim 11, wherein a chemical mechanicalpolishing process is applied to remove the portion of the metal layeroutside the second opening and the third opening to form the seconddamascene electrode layer and the dual damascene structure.
 13. Themethod as claimed in claim 11, wherein the metal layer is a copperlayer.